`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineers: Brentton Garber, Georgii Tkachuk
// 
// Create Date:    15:10:14 02/27/2013 
// Design Name: button_handler
// Module Name: button_handler 
// Project Name: Lab 1
// Target Devices: Xilinx Spartan6 XC6LX16-CS324 
// Tool versions: Xilinx ISE 14.2 
// Description: 
//
// Dependencies: none
//
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module button_handler(o_positive_edge,
							 o_positive_toggled,
							 o_negative_edge,
							 o_negative_toggled,
							 i_switch,
							 i_clk,
							 i_reset_b
);

input wire i_switch, i_clk, i_reset_b;
output wire o_positive_edge, o_positive_toggled, o_negative_edge, o_negative_toggled;

wire w_hys, w_ped, w_ned, w_tff_1, w_tff_2;

sig_hys sig_hys(.fil_sig(w_hys), .clk(i_clk), .reset_b(~i_reset_b), .dir_sig(i_switch));
PED i_ped(w_hys, i_clk, ~i_reset_b, w_ped);
NED i_ned(w_hys, i_clk, ~i_reset_b, w_ned);
TFF i_tff_1(w_ped, i_clk, ~i_reset_b, w_tff_1);
TFF i_tff_2(w_ned, i_clk, ~i_reset_b, w_tff_2);

assign o_positive_edge = w_ped;
assign o_positive_toggled = w_tff_1;
assign o_negative_edge = w_ned;
assign o_negative_toggled = w_tff_2;

endmodule
